外企招聘数字电视芯片研发人才

公司是由在研发、设计、运营和生产电视解码芯片方面具有丰富经验的半导体专家创办的。管理团队由Aegeus前首席运营官刘明，Genesis Microchip (NASDAQ:GNSS)前首席技术官董旭，UT斯达康(NASDAQ:UTSI)的前首席技术官于燕斌，LSI Logic (NASDAQ:LSI)中国区前总经理马明组成。管理团队在电视芯片设计方面拥有超过20年的经验，并在这一领域内拥有40项专利。


招聘负责人:conny
电话：０１０-８５１８５６９０-６５０
E-mail:he.yan@fesco.com.cn
MSN:CONNY_0919@FESCO.COM.CN


算法和软件工程师
薪资：15000-25000元/月           人数：5          需到岗时间：   
职位描述：
1．  协助硬件工程师规范芯片模块功能，研发算法，模块结构及C-modal 验证。
2．  制作多种测试码流及标准响应数据供芯片模块模拟测试
3．  参与嵌入式操作系统调试及应用软件开发，包括MPEG-2视频解码及多种音频格式解码软件开发
4．  GUI开发及整机系统调试。
任职要求：
1、  对MPEG 1,2,4和H.264等其它现代数字视频音频压缩编码技术及定义有深刻的了解和丰富的经验；
2、  理想的应征者应该熟悉电脑编程语言，C/C++和汇编，并有C-Modeling应用软件、硬件设计和嵌入式系统的设计经验。
3、  应征者应有硕士或博士学位，拥有相应的英语水准
4、  有3 - 5年的工作经验者优先
5、  热爱团队工作，勇于接受挑战，享受开发产品的乐趣

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芯片硬件设计工程师
薪资：15000-25000元/月           人数：  7        需到岗时间：
职位描述：   
1、  数字逻辑模块的微结构和c-modeling
2、  DTV SOC 中数字逻辑模块的设计，仿真，综合和时基分析.
3、  完成领导交给的任务。
任职要求：
1、  具有芯片硬件设计经验，熟悉Verilog及其脚本语言。
2、  能够熟练使用VLSI 的设计工具进行芯片硬件的设计、验证、综合，以及时基分析。
3、  理想的应征者应熟悉ASIC设计流程中的各个方面，包括设计规格、框架设计、仿真、原型设计、时基分析、ECO，以及系统调试，并熟悉C语言、电脑结构、图形、和视频压缩技术。
4、  应征者需有学士学位，拥有相应的英语水准
5、  有5年以上的工作经验者优先考虑
6、  热爱团队工作，勇于接受挑战，享受开发产品的乐趣

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HW Design Manager


Salary Range: 20000RMB to 30000RMB/month  Number of Positions: 2
Job description:
1、The candidate is expecting to lead the SOC hardware product development team with responsibilities that include product definition, development, verification, testing, customer support and silicon bring up, etc.

2、The candidate will play the role of providing technical leadership to the team as well as being an individual contributor for some identified key tasks. He/She will be responsible for the overall growth, nurturing and mentoring of the team. The candidate will have to frequently interact with our software team.
skills
1、An ideal candidate will have experience in all facets of ASIC design flow such as RTL coding, verification, DFT, timing analysis, synthesis and place and route besides having a thorough understanding of issues encountered in the implementation of deep sub micron designs. Involvement in a few large tape-outs as technical lead/individual contributor is a definite plus.


2、The candidate should be experienced with MPEG 1, 2, H.264, and other modern digital video/audio compression algorithms and specifications; former experience to tape out the similar chips is a strong plus.

3、The candidate will have Bachelor of Engineering/Master of engineering in Electrical engineering with relevant minimum experience of 5 years ( 10 + years preferred) with at least the last three years as technical leader. US Silicon Valley working experience preferred. He/She should possess excellent written and verbal English/Chinese communication skills.



SW Design Manager


Salary Range: 20000RMB to 30000RMB     Number of Positions: 2
job description:
1、The candidate is expecting to lead the SOC software product development team with responsibilities that include product definition, development, verification, testing, customer support and silicon bring up, etc.

2、The candidate will play the role of providing technical leadership to the team as well as being an individual contributor for some identified key tasks. He/She will be responsible for the overall growth, nurturing and mentoring of the team. The candidate will have to frequently interact with our hardware team.
skills:
1、An ideal candidate will have experience in all facets of ASIC driver and application level design flow such as strong experience of product design in consumer electronic field, strong capacity of specification/standard analysis and design, background of RTOS(Real-time Operating System) and embedded system, including Linux, NuclearPlus and Vxworks, capability of software architecture design for embedded/home-media system, knowledge of software refactory and proficient programming ability in C, PERL, GNU-MAKE, ASM. Involvement in a few large tape-outs as technical lead/individual contributor is a definite plus.


2、The candidate should be experienced with MPEG 1, 2, H.264, and other modern digital video/audio compression algorithms and specifications; former experience to program and support the similar chips is a strong plus.

3、The candidate will have Bachelor of Engineering/Master of engineering in Electrical engineering with relevant minimum experience of 5 years ( 10 + years preferred) with at least the last three years as technical leader. US Silicon Valley working experience preferred. He/She should possess excellent written and verbal English/Chinese communication skills.

那我还是考研吧!